Simplified Electronics Department : 2016

Sunday, 3 July 2016

Test Bench

whenever you need to store value you use reg
and whenever you have to just keep value you use wire

from test bench when you provide inputs then you can say that you have provided stimulas

If you see the above diagram you can see that you have to provide your stored value as input in your design module so you are bouded to use reg

whereas for analyzing the output you have to use wire

You should know that tool is use tool is use to see the simulation

`include "and2.v" //we extenstion is must .v symbol

`timescale 1ns/100ps

this means it will consider #10 as 10 ns

`define clockperiodby2 10 //10ns half period is 50MHz
in above define commad you can use any name

the define command is use to assign this delay anywhere you like.For eg

clockperiodby2 clk=!clk;

when you sythesis your code in fpga you just burn design and thus there is no meaning of hash delay's .obivously as test benches are just an another way to test ur design through simulation other than FPGA. Anyway i also admity FPGA is more fun full way of testing your circuit.

It is safe to send data before posedge if you have it in your sensitiity list .Sending data after posedge makes no use

In always block you must use blocking assignment i.e <= and not "=" .However you can use any in intial block

Common Mistakes while writting test bench

Spelling of Initial

Ignoring Begin end

Anyway there are many beautiful way's of checking simulation

Using System Verilog {costilier way}--tools are crossing 1 lakh rupee

System C [Inspire from Circuit Sutra]---Basically company works on finding Verification Methodoly for Hardware design

Python scripts [Inspire from Here]

Tuesday, 21 June 2016

Inside CPU

Free Electricity at home

Telecome Industry Never tell you about the free electricity that they provide in your telephone lines

Wednesday, 8 June 2016

COUNTERS

WHY COUNTERS ?

Ans. As clock just generate a pulse similarly counter generates a counting with the help of this pulse.

Note: In counter's we go from LSB to MSB Q0--Q3
and while writing a sequence from waveform write carefully from MSB --LSB Q3--Q0

ASYNCHRONOUS COUNTER
--These are also Known as Ripple Counter
--As there is a more delay compared to synchronous there fore there comes a gliches in its waveforms
--Moreover in Asynchronous counter there is no combinational circuit in input so here
Tclk>=Tc-->q

Unlike synchronous counter having Tclk>=Tc-->q + Tpd(propogation delay of combination logic)

--In Asynchronous while making waveforms we have to just see the +ve edge of clock
whereas
In Synchronous you also have to see waveform of input of flipflop combinational logic apart from +ve edge of clock.

SYNCHRONOUS COUNTERS

These counters saves us from glitch waveforms all outputs in these are having same delay

--FSM
--MOD COUNTER
--EVEN COUNTER
--ODD COUNTER

3-BIT SYNCHRONOUS COUNTER

4-bit Synchronous Counter

Difficult Synchronous Counter

Tuesday, 31 May 2016

TPU

TPU (Tensor Processing Unit)

-->Google has said that this device is far away better than CPU,GPU,FPGA's.
-->This is far better from above devices as it uses less transistor per unit watt
-->But contrary some blogs says at same time it occupies more power
-->This is use to develop custom hardware
-->This will be attached to the Hardisk's at Google data centre
-->One can develop custom Hardware's Using these TPU access through cloud i guess.
-->Google street view and its deep mind technology Alpha Go (Chinese Game that represent human brain) works on this TPU.
--> It is 7 generation higher than More's Law
-->It is develop with an requirnment that great softwares needs beautiful hardware
-->It is discussed in I/O conference Google by CEO sundar pichai

Reference :-Google Blog

Watch Last few minutes of speech by CEO Sundar Pichai in below video

Sunday, 22 May 2016

Interfaces (I2C ,SPI, RS232)

Interfaces are the protocols that are required by the devices to interact. Some of the common Interfaces are I2C,SPI,RS232 Interface.

Among three interface SPC is fastest after that comes I2C and finally RS232 which not has any clock. Watch below video to gain practical Knowledge too about above mentioned interfaces.Arduino has inbuilt SPC,I2C interface. and Raspberrypi has inbuilt all interfaces.

In below Video Ben Heck

Used SPC--to interface distance sensor with arduino

Used I2C--to interface temperature sensor with arduino

Used RS232--to interface Speaker using chip which too interfaced with the chip of RS232 which finally connected to computer where command were desired words were written to hear one by user.

Watch Below Video for better Understanding.

UART

Adding UART(Universal Asynchronous Receiver Transceiver

For More Information [Click Here]

UART
--UART is the universal Asynchronous Receiver Transiver
--It is the protocol is a self-syncronizer that is without synchronous clock with host (transceiver) the data automatically sends to the receiver.

To Understand the protocol of UART you should understand following terms

SPI Interface (Serial Peripheral Interface)--It is the protocol made by motorolla .this is a 4 wire serial communication .use to transfer data from peripheral to microcontroller/microprocessor or b/w microprocessor to microprocessor

For More Info [Click Here]

FIFO MODE(First in First Out Mode)--It is the mode that is use in

For More Info [Click Here]

For More Knowledge from eye of chip designer Visit [Click Here] (Given Text in very interesting way)

Clock

Clock is the heart of any electronics hardware device that calculates,provides delay etc.Clock is essential in every hardware that needs a repetion like generating a ramp wave in multimeter, increasing or decressing a speed of processor, It is use almost in every device.

Clock is given using crystal oscillator, cmos ic etc.

Clock can be understanded better by student and bell example in schools

In Processor Clock impacts speed in following ways

---Raising a clock

---Dividing a clock by some factor (>1 i guess) i guess---gives more no. of cycles(Combination of each tick(1) tack(0) is known as cycle)-->fasten the speed

---Multiplying a clock by some factor (>1 i guess)---gives less no. of clock cycles (I guess if multiplication factor is greater than 1.obviously ! if it is less than 1 then it would indirectly be a division ...decimal removed ..no go down ...lab ! lab!. --> ultimately in these as time period increases therefore,no of clocks come after huge huge interval -->and thus speed reduces.

there are also many other factors to increase speed of processor beside clock like

--Pipelining
--Parllelism
--Increasing Cores of CPU
--Increasing No. of bits like make a 64 bit ......the advantage of this reflects in high end graphics games....and not much in small programs....that is by increasing number of bits you mean to increase the data rate at a fix interval of time

For Detailed Knowledge [Click Here]

Thursday, 19 May 2016

FSM

In above code you have maded two always{procedural} blocks because your “y” {past state} is a level sensitive in first always block and negedge clk is the edge triggered in your second always procedural block therefore,it is a rule you can’t write both edge triggered as well as level triggered in same sensitivity list.

Wednesday, 18 May 2016

What Happen when Boil eggs on CPU

For Simulation Click Here

Sunday, 15 May 2016

Analysis of Timing Diagram in LCD Driver

Watch from 5:37

Kinds of Signal While Analyzing a Waveforms

Differntial Pair Signalling

you can see here we mix two different kinds of waves in it .

Why we use these kinds of signal?

Ans. Because you get much higher speed with these signals

Top Channels for Electronics Engineer

1.For Techical Seminars
CCCen

2.For Projects
Ben Heck Show

PSHDL

You can do PSHDL coding in cloud itself

In PSHDL if you just write

module MyFirstModule{
register uint<17> counter=counter+1;
}

it means the system will count at rising edge of every count

But in case you want a register to count at falling edge then in that case you have to write code as follow:-

1) Adding a Two Number using PSHDL

Do you Know How Actually Simulation is coming out on Browser? The answer to this is you have converted your code into javascript.

2) Making a Counter Using PSHDL

module MyFirstModule{
register uint<17> counter=counter+1;
out bit led=counter(13);
}

And your output will be blinking led as shown on that screen

Now you can yourself see How simple is this PSHDL

Sunday, 24 April 2016

Hexadecimal operations

Bit rate Vs Baud Rate

In digital Communication our Intention is to transfer Digital Data which is obviously seen in bit and therefore for that we use the term bit rate.

But As we can't send this digital data directly so for that we have to convert this digital data into some sought of signal and that is achieved by line coding techniques like NRZ, Manchester coding ....etc etc.
Now when we talk about speed here in sense of this signal then we talk about baud rate which is also known as pulse rate/ modulation rate/ baud rate or simply baud.

You can also make a analogy of above concept as by a example of train where each carrier of a train is the signal element (baud) and passenger sitting inside that carrier is a data element (bit).
similarly signal rate (baud rate) and data rate(bit rate)

For Higher efficieny bit rate > baud rate
and To increase this efficiency only we have many line coding techniques

Formula for Baud rate is

Baud Rate = Bit rate
------------
No. of data element carried by each signal element

There is some examples also for detail Understanding
For that [Click Here]

Saturday, 23 April 2016

CPU VS FPGA VS ASIC

CPU---SOFTWARE--LIST OF INSTRUCTIONS
FPGA--FIRMWARE--GATES---PROGRAMED WITH THE HELP OF VERILOG,VHDL
ASIC--IT CAN BE USED AS FPGA BUT NOT REPROGRAMMED

it means you will test your design on fpga practically verify it and then give chip manufacturing industry to manufacture a chip.

Friday, 22 April 2016

Microprocessor 8085 Verilog

/*module processor(a,b, );
input [2:0]opcode;
input a,b;
output o;
case(opcode)
begin
000: assign o<=a+b;
001: assign o<a-b;
010: assign
*/
module meomory(addr,,enable,out);
input [2:0]addr; //pc
output reg [10:0] out;
reg [10:0]mem[7:0];
input enable; //read
initial
$readmemb("input.txt",mem);
always @(*)
if(enable)
out=mem[addr];
else
out=out;
endmodule
module ir(a,en,out);
input [10:0]a;
input en;
output reg [10:0]out;
always @(*)
begin
if(en==1)
out=a;
end
endmodule
module decoder(in,en,opcode,data);
input [10:0]in;
input en;
output reg [2:0]opcode;
output reg[7:0]data;
always @(*)
begin
if(en==1)
begin
opcode=in[10:8];
data=in[7:0];
end
/*else
begin
opcode=0;
data=0;
end*/
end
endmodule
//module meomory_tb;
// reg [3:0]addr;
// reg enable;
module ir_tb;
reg [10:0]a;
reg en;
wire [10:0]out;
ir v1(a,en,out);
initial
begin
#1 en=1;
#5 a=11'b10001100110;
#10 en=0;
#11 a=11'b01011001101;
end
endmodule
module decoder_tb;
reg [10:0]in;
reg en;
wire [2:0]opcode;
wire [7:0]data;
decoder v2(in,en,opcode,data);
initial
begin
#1 en=1;
#5 in=11'b10001100110;
#10 en=0;
#11 in=11'b01011001101;
end
endmodule
module alu4pro(opcode,vala,valb,aluout);
input [2:0]opcode;
input [7:0]vala;
input [7:0]valb;
output reg [10:0]aluout;
parameter add_op=3'b000,sub_op=3'b001,nand_op=3'b010,nor_op=3'b011,xor_op=3'b100,and_op=3'b101,or_op=3'b110,xnor_op=3'b111;
always @(*)
case(opcode)
add_op: begin
aluout=vala+valb;
end
sub_op:begin
aluout=vala-valb;
end
nand_op:begin
aluout=~(vala&valb);
end
nor_op:begin
aluout=~(vala|valb);
end
xor_op:begin
aluout=vala^valb;
end
and_op:begin
aluout=vala&valb;
end
or_op:begin
aluout=vala|valb;
end
xnor_op:begin
aluout=~(vala^valb);
end
endcase
endmodule
module alu4pro_tb;
reg [2:0]opcode;
reg [7:0]vala;
reg [7:0]valb;
wire [10:0]aluout;
alu4pro b2(opcode,vala,valb,aluout);
initial
begin
opcode=3'b000;
vala=3'b10;
valb=3'b11;
#20opcode=3'b110;
vala=3'b111;
valb=3'b101;
end
//$monitor("time=%d,opcode=%b,vala=%b,valb=%b,aluout=%b",$time,opcode,vala,valb,aluout);
endmodule
module accumulator(aluout,clk,rst,accout);
input [7:0]aluout;
input clk;
input rst;
output reg [7:0]accout;
always@(clk)
if(rst)
begin
accout=aluout;
end
else
accout=0;
endmodule
module accumulator_tb;
reg [7:0]aluout;
reg clk;
reg rst;
wire [7:0]accout;
accumulator b3(aluout,clk,rst,accout);
initial
begin
clk=0;
rst=1;
aluout=6'b101011;
#10 rst=0;
#15 rst=1;
end
always #5 clk=~clk;
endmodule
/*module controller();
output reg rd,rw,de,en;
reg ps,ns;
input clk,rst;
always @(clk)
*/
module controller(rst,clk,read,addr,fe,de,ex);
input rst,clk;
reg [2:0]ps;
reg [2:0]ns;
output reg read,fe,de,ex;
parameter fetch=3'b000,decode=3'b001,execute=3'b010;
output reg [3:0]addr=4'b0000;
always @(posedge clk ,posedge rst)
if (rst)
ps<=fetch;
else
ps<=ns;
always @(clk)
case(ps)
fetch: begin
read=1;
fe=0;
de=0;
ex=0;
end
decode:begin
read=0;
fe=0;
de=1;
ex=0;
end
execute:begin
read=0;
addr=addr+1;
fe=0;
de=0;
ex=1;
end
endcase
endmodule
module controller_tb;
reg rst,clk;
//reg[2:0]ns;
wire read;
wire fe,de,ex;
controller b1(rst,clk,read,fe,de,ex);
initial
begin
clk=0;
rst=0;
#10 rst=1;
#12 rst=0;
// #2 ns=3'b001;
end
always #5 clk=~clk;
endmodule
module processor(rst,clk,inp,outp);
input rst;
input clk;
input [10:0]inp;
output [10:0]outp;
wire accout;
wire rd;
wire ex;
wire de;
wire read;
wire addr; //pc
wire mout; //meomory output
wire opcode;
meomory hk1(addr,read,mout); //read=enable
ir hk2(mout,rd,out); //rd-enable mout-a
decoder hk3(out,de,opcode,data); //de-enable
alu4pro hk4(opcode,inp,accout,aluout); //decoder ka de 8bit data kaise use karon !!!! pehle hi ek acc se i/p ek main i/p donga is module se dusra i/p decoder wale ka kya karonga ...refer to diagram
accumulator hk5(outp,clk,ex,accout); //ex-rst
controller hk6(rst,clk,read,addr,fe,de,ex);
endmodule
module processor_tb;
reg rst,clk;
reg[7:0]inp;
wire [7:0]outp;
processor hk10(rst,clk,inp,outp);
initial
begin
rst=0;
clk=0;
#2 inp=8'b01110101;
#5 rst=1;
#7 rst=0;
end
always #10 clk=~clk;
endmodule