Friday, 15 April 2016

Error Checking Techniques in Data link Layer

In any communication system there is layer in the top-bottom order in one device shown below

1) Application Layer-encryption
2)Presentation Layer
3)Session Layer-check till how many pages data has sended properly
4)Transport Layer-convert big files to small messages
5)Network Layer-it adds source and destination addresses
6)Data Link Layer-it check error and also further break the messages
7)Physical Layer-Here coding techniques like NRZ-L,NRZ-M,NRZ-S,Biphase-L(Manchester                                          coding),Biphase-M,Biphase s,Bipolar NRZ, Unipolar NRZ etc etc happen here.

at each there there is some memory containing | H | Data | T | i.e Header data tail is updated which finally have to send

Similarly other device say another mobile phone will have these layers in order

Between these devices there is a routers in which communication happen through packet switching,circuit switch,store and forward switching etc etc.

Communication Happening Between one device to another is termed as end to end communication

and Communicative Happening Between router to one particular device is Known as link to link communication.error checking,network checking happen link to link only .you thick yourself if it happens end to end how much time it have taken.Actually Every layer is linked by link to link connection i.e

Session Layer--SLP
Tansport Layer-TLP
in above short forms P stands for protocol similarly others also have some name ..search about it..

In Data Link Layer there are Many Error checking techniques
these are as follow
1)Even parity
2)Odd Parity
3)Cycle redundancy check
4)Bit Stream check-in this we divide by no. of bits and put some remainder and then store this data in                                  tail and send.
5)check sum
and etc etc.


ODD Parity
XOR gate is a ODD parity checker as if there is a odd number of 1's then output gets 1(HIGH)
in veriog you apply XOR operation as ^(100011100)

A     B    OUT
0      0       0          <--Even No of  1  
0      1       1          <--Odd  No of  1    Output--1
1      0       1          <--Odd  No of  1    Output--1
1      1       0          <--Even No of  1    

Even Parity
XNOR gate is a Even parity checker as if there is a even number of 1's then output gets 1(HIGH).
in verilog you apply XNOR operation as ~^(100001111)

A     B    OUT
0      0       1          <--Even No of  1      Output--1
0      1       0          <--Odd  No of  1    
1      0       0          <--Odd  No of  1
1      1       1          <--Even No of  1       Output--1



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